// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX : 
// IP Name      : 
//                
// File name    :axis_data_fifo(with out fwft fifo)
// Module name  : 
// Full name    :
//
// Author       :  Hbing 
// Email        :  2629029232@qq.com
// Data         :  2020/8/24
// Version      :  V 1.0 
// 
//Abstract      :
// Called by    :  Father Module
// 
// Modification history
// ------------------------------------------------------------------------------------------------------
// 
//  
// *********************************************************************
 `include "top_define.v"
// `define CONV_SIM
// *******************
// *******************
// DESCRIPTION
// *******************
// 10G接收处的axis跨时钟fifo
// clk 312.5 -> 156.25 or 312.5 -> 630
// axi_data_width 256 -> 64
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 

module axis_conv_tx_40(

	input  wire				s_axis_areset 	,
	input  wire  			s_axis_aclk 	,
    input  wire [11:0]      ram_dp_cfg_register,
		
	input  wire 			s_axis_tvalid	,
	output wire 			s_axis_tready	,
	input  wire [255:0]		s_axis_tdata 	,
	input  wire [ 31:0]		s_axis_tkeep 	,
	input  wire 			s_axis_tlast 	,
		
	input  wire 			m_axis_aclk 	,
	input  wire 			m_axis_areset 	,
		
	output reg  			m_axis_tvalid 	,
	input  wire 			m_axis_tready 	,
	output reg  [63:0]		m_axis_tdata  	,
	output reg  [ 7:0]		m_axis_tkeep  	,
	output reg  			m_axis_tlast  	
	//output wire [ 6:0]		m_axis_tuser  	
	);

//*******************
//DEFINE PARAMETER
//*******************
//Parameter(s) 

//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS

reg 			s_axis_tvalid_sample		;
reg [255:0]		s_axis_tdata_sample 		;
reg [ 31:0]		s_axis_tkeep_sample 		;
reg 			s_axis_tlast_sample 		;
reg 			s_axis_tfirst_sample 		;

//做成AB备份
reg 			update_A 						;
reg 			m_axis_tfirst_fifo_reg_A 		;
reg 			m_axis_tvalid_fifo_reg_A		;
reg [255:0]		m_axis_tdata_fifo_reg_A 		;
reg [ 31:0]		m_axis_tkeep_fifo_reg_A 		;
reg 			m_axis_tlast_fifo_reg_A 		;
reg 			m_axis_trans_en_reg_A 			;
// reg 			m_axis_empty_fifo_reg_A 		;

reg 			m_axis_tvalid_fifo_reg_B		;
reg 			m_axis_tfirst_fifo_reg_B 		;
reg [255:0]		m_axis_tdata_fifo_reg_B 		;
reg [ 31:0]		m_axis_tkeep_fifo_reg_B 		;
reg 			m_axis_tlast_fifo_reg_B 		;
reg 			m_axis_empty_fifo_reg_B 		;


reg 			m_axis_tfirst_fifo_dl 	;
reg 			m_axis_tvalid_fifo_dl	;
reg [255:0]		m_axis_tdata_fifo_dl 	;
reg [ 31:0]		m_axis_tkeep_fifo_dl 	;
reg 			m_axis_tlast_fifo_dl 	;
reg 			m_axis_empty_fifo_dl 	;
// reg 			fifo_dl_updating 		;

reg 			m_axis_tfirst_fifo_reg 	;
reg 			m_axis_tvalid_fifo_reg	;
reg [255:0]		m_axis_tdata_fifo_reg 	;
reg [ 31:0]		m_axis_tkeep_fifo_reg 	;
reg 			m_axis_tlast_fifo_reg 	;

// reg 			fifo_empty_dl 				;
reg [ 1:0] 		width_change_step 			;
reg 			fifo_we 					;
reg 			fifo_rd 					;	
reg 			fifo_rd_dl 					;
reg 			fifo_rd_dll 				;

`ifdef CONV_SIM
reg [3:0]		rand_empty_val_cnt 			;
reg 			rand_empty_val 				;
reg 			rand_empty 					;
reg 			rand_empty_dl 				;
`endif
	
//WIRES
wire [290:0] 	fifo_din 				;
wire [290:0] 	fifo_dout  				;
wire 			fifo_empty 				;
wire 			fifo_full 				;
wire  			update_dl_req 			;
wire 			update_B 				;

wire 			m_axis_tvalid_fifo		;
wire 			m_axis_tfirst_fifo 		;
wire [255:0]	m_axis_tdata_fifo 		;
wire [ 31:0]	m_axis_tkeep_fifo 		;
wire 			m_axis_tlast_fifo 		;

wire 			m_axis_tfirst_fifo_sample 	;
wire 			m_axis_tvalid_fifo_sample	;
wire [255:0]	m_axis_tdata_fifo_sample 	;
wire [ 31:0]	m_axis_tkeep_fifo_sample 	;
wire 			m_axis_tlast_fifo_sample 	;
//*********************
//INSTANTCE MODULE
//*********************
assign fifo_din = {s_axis_tfirst_sample,s_axis_tlast_sample,s_axis_tvalid_sample,s_axis_tkeep_sample,s_axis_tdata_sample};
assign {m_axis_tfirst_fifo,m_axis_tlast_fifo,m_axis_tvalid_fifo,m_axis_tkeep_fifo,m_axis_tdata_fifo} = fifo_dout[290:0];
assign s_axis_tready = ~fifo_full;
`ifdef ASIC
asyn_fifo_nw256_nb291 #(.L(8),.DW(291))
U_asyn_fifo_nw256_nb291 (
	.clka(s_axis_aclk),
	.clkb(m_axis_aclk),
    .ram_dp_cfg_register(ram_dp_cfg_register),
	.clr(s_axis_areset),
	.w_data(fifo_din),
	.w_we(fifo_we),
	.w_full(),
	.w_afull(fifo_full),
	.r_data(fifo_dout),
	.r_re(fifo_rd),
	.r_empty(fifo_empty),
	.r_aempty()
	);
`else
asyn_fifo_nw256_nb291 U_asyn_fifo_nw256_nb291(
	.wr_clk 		(s_axis_aclk 		 	),
	.wr_rst 		(~s_axis_areset 	 	),
	.din 			(fifo_din 			 	),
	.wr_en			(fifo_we 				),
	.full 			(/*fifo_full*/ 			),
	.prog_full 		(fifo_full 				),
	.rd_clk 		(m_axis_aclk 			),
	.rd_rst 		(~m_axis_areset 	 	),
	.dout			(fifo_dout 				),
	.rd_en 			(fifo_rd 			 	),
	.empty 			(fifo_empty 			)
	);
`endif
//*********************
//MAIN CORE
//*********************

`ifdef CONV_SIM
always @(posedge m_axis_aclk or negedge m_axis_areset) begin : rand_empty_val_gen
	if (~m_axis_areset) begin
		// reset
		rand_empty_val 	<=  	1'b1;
	end
	else if(m_axis_tlast_fifo) begin
		rand_empty_val 	<= 1'b1;
	end
	else if(rand_empty_val_cnt == 4'b1) begin
		rand_empty_val 	<=  	1'b0;
	end
	else begin
		rand_empty_val 	<= rand_empty_val;
	end
end

always @(posedge m_axis_aclk or negedge m_axis_areset) begin : rand_empty_gen
	if (~m_axis_areset) begin
		// reset
		rand_empty 		<=    	1'b0;
	end
	else if(fifo_rd & rand_empty_val) begin
		rand_empty 	<= ~|({$random} % 4);
	end
	else if(rand_empty_val_cnt == 4'b1) begin
		rand_empty 	<= 		1'b0;
	end
	else begin
		rand_empty 	<= rand_empty;
	end
end

always @(posedge m_axis_aclk or negedge m_axis_areset) begin : rand_empty_dl_gen
	if (~m_axis_areset) begin
		// reset
		rand_empty_dl 	<=  	1'b0;
	end
	else begin
		rand_empty_dl 	<= rand_empty;
	end
end


always @(posedge m_axis_aclk or negedge m_axis_areset) begin : rand_empty_continue_cnt
	if (~m_axis_areset) begin
		// reset
		rand_empty_val_cnt 	<= 4'b0;
	end
	else if(rand_empty && (~rand_empty_dl) && rand_empty_val) begin
		rand_empty_val_cnt 	<= 4'd2;
	end
	else if(|rand_empty_val_cnt) begin
		rand_empty_val_cnt 	<= rand_empty_val_cnt - 4'd1;
	end
	else begin
		rand_empty_val_cnt 	<= rand_empty_val_cnt;
	end
end

`endif
//assign m_axis_tuser = 7'h20;

always @(posedge s_axis_aclk or negedge s_axis_areset) begin : sample_axi_stream
	if (~s_axis_areset) begin
		// reset
		s_axis_tvalid_sample 	<=    1'b0;
		s_axis_tdata_sample  	<= 	256'b0;
		s_axis_tkeep_sample  	<=   32'b0;
		s_axis_tlast_sample  	<=    1'b0; 
		s_axis_tfirst_sample 	<=    1'b0;
		fifo_we 				<= 	  1'b0;
	end
	else if(s_axis_tready) begin
		s_axis_tdata_sample 	<= s_axis_tdata 	;
		s_axis_tkeep_sample		<= s_axis_tkeep 	;
		s_axis_tlast_sample		<= s_axis_tlast 	;
		s_axis_tvalid_sample 	<= s_axis_tvalid 	;
		s_axis_tfirst_sample 	<= s_axis_tvalid & (~s_axis_tvalid_sample);
		fifo_we 				<= s_axis_tvalid	;
	end
	else begin
		s_axis_tdata_sample 	<= s_axis_tdata_sample 	;
		s_axis_tkeep_sample		<= s_axis_tkeep_sample	;
		s_axis_tlast_sample		<= s_axis_tlast_sample	;
		s_axis_tvalid_sample 	<= s_axis_tvalid_sample ;
		s_axis_tfirst_sample 	<= s_axis_tfirst_sample ;
		fifo_we 				<= 1'b0 				;
	end
end
always @(posedge m_axis_aclk or negedge m_axis_areset) begin : store_data_of_fifo
	if (~m_axis_areset) begin
		// reset
		m_axis_empty_fifo_dl 	<=    1'b1;
	end
	else if(fifo_rd_dl) begin
		m_axis_empty_fifo_dl	<= 	  1'b0; 	
	end
	else if(update_B) begin
		m_axis_empty_fifo_dl 	<= 	  1'b1;
	end
	else begin
		m_axis_empty_fifo_dl 	<= 	m_axis_empty_fifo_dl;
	end
end

always @(posedge m_axis_aclk or negedge m_axis_areset) begin : val_store_data_of_fifo
	if (~m_axis_areset) begin
		// reset
		m_axis_tvalid_fifo_dl 	<=    1'b0;
		m_axis_tdata_fifo_dl  	<= 	256'b0;
		m_axis_tkeep_fifo_dl  	<=   32'b0;
		m_axis_tlast_fifo_dl  	<=    1'b0; 
		m_axis_tfirst_fifo_dl 	<= 	  1'b0;
		// fifo_empty_dl 			<=    1'b1;
		fifo_rd_dl 				<=    1'b0;
		fifo_rd_dll 			<= 	  1'b0;
	end
	else begin
		m_axis_tdata_fifo_dl 	<= m_axis_tdata_fifo 	;
		m_axis_tkeep_fifo_dl	<= m_axis_tkeep_fifo	;
		m_axis_tlast_fifo_dl	<= m_axis_tlast_fifo	;
		m_axis_tvalid_fifo_dl 	<= m_axis_tvalid_fifo 	;
		m_axis_tfirst_fifo_dl 	<= m_axis_tfirst_fifo 	;
		// fifo_empty_dl 			<= fifo_empty 			;	
		fifo_rd_dl 				<= fifo_rd 				;
		fifo_rd_dll 			<= fifo_rd_dl 			;
	end
end

always @(posedge m_axis_aclk or negedge m_axis_areset) begin : val_store_data_of_fifo_dl
	if (~m_axis_areset) begin
		// reset
		m_axis_tvalid_fifo_reg 	<=    1'b0;
		m_axis_tdata_fifo_reg  	<= 	256'b0;
		m_axis_tkeep_fifo_reg  	<=   32'b0;
		m_axis_tlast_fifo_reg  	<=    1'b0; 
		m_axis_tfirst_fifo_reg 	<= 	  1'b0;
	end
	else if(fifo_rd_dll) begin
		m_axis_tdata_fifo_reg 	<= m_axis_tdata_fifo_dl 	;
		m_axis_tkeep_fifo_reg	<= m_axis_tkeep_fifo_dl		;
		m_axis_tlast_fifo_reg	<= m_axis_tlast_fifo_dl		;
		m_axis_tvalid_fifo_reg 	<= m_axis_tvalid_fifo_dl 	;
		m_axis_tfirst_fifo_reg 	<= m_axis_tfirst_fifo_dl 	;
	end
	else begin
		m_axis_tdata_fifo_reg 	<= m_axis_tdata_fifo_reg 	;
		m_axis_tkeep_fifo_reg	<= m_axis_tkeep_fifo_reg	;
		m_axis_tlast_fifo_reg	<= m_axis_tlast_fifo_reg	;
		m_axis_tvalid_fifo_reg 	<= m_axis_tvalid_fifo_reg 	;
		m_axis_tfirst_fifo_reg 	<= m_axis_tfirst_fifo_reg 	;
	end
end

assign m_axis_tdata_fifo_sample  = (fifo_rd_dll)? m_axis_tdata_fifo_dl  : m_axis_tdata_fifo_reg ;
assign m_axis_tkeep_fifo_sample  = (fifo_rd_dll)? m_axis_tkeep_fifo_dl	: m_axis_tkeep_fifo_reg ;
assign m_axis_tlast_fifo_sample  = (fifo_rd_dll)? m_axis_tlast_fifo_dl	: m_axis_tlast_fifo_reg ;
assign m_axis_tvalid_fifo_sample = (fifo_rd_dll)? m_axis_tvalid_fifo_dl : m_axis_tvalid_fifo_reg;
assign m_axis_tfirst_fifo_sample = (fifo_rd_dll)? m_axis_tfirst_fifo_dl : m_axis_tfirst_fifo_reg;


always @(posedge m_axis_aclk or negedge m_axis_areset) begin : read_fifo
	if (~m_axis_areset) begin
		// reset
		fifo_rd 	<=    	1'b0;
	end 
	`ifdef CONV_SIM
	else if((update_dl_req) & (~fifo_empty) & (~rand_empty)) begin
	`else
	else if((update_dl_req) & (~fifo_empty)) begin
	`endif
		fifo_rd 	<=		1'b1;
	end
	else begin
		fifo_rd 	<= 		1'b0;
	end
end

assign update_dl_req = ((update_B | m_axis_empty_fifo_dl) & (~fifo_rd) & (~fifo_rd_dl));
assign update_B  	 = ((update_A | m_axis_empty_fifo_reg_B) & (~m_axis_empty_fifo_dl));

always @(posedge m_axis_aclk or negedge m_axis_areset) begin : store_data_in_B
	if (~m_axis_areset) begin
		// reset
		m_axis_tvalid_fifo_reg_B 	<=    1'b0;
		m_axis_tdata_fifo_reg_B  	<= 	256'b0;
		m_axis_tkeep_fifo_reg_B  	<=   32'b0;
		m_axis_tlast_fifo_reg_B  	<=    1'b0; 
		m_axis_tfirst_fifo_reg_B 	<= 	  1'b0;
	end
	else if(update_B) begin
		m_axis_tdata_fifo_reg_B 	<= m_axis_tdata_fifo_sample		;
		m_axis_tkeep_fifo_reg_B		<= m_axis_tkeep_fifo_sample		;
		m_axis_tlast_fifo_reg_B		<= m_axis_tlast_fifo_sample		;
		m_axis_tvalid_fifo_reg_B 	<= m_axis_tvalid_fifo_sample 	;
		m_axis_tfirst_fifo_reg_B 	<= m_axis_tfirst_fifo_sample 	;
	end
	else begin
		m_axis_tdata_fifo_reg_B 	<= m_axis_tdata_fifo_reg_B 	;
		m_axis_tkeep_fifo_reg_B		<= m_axis_tkeep_fifo_reg_B	;
		m_axis_tlast_fifo_reg_B		<= m_axis_tlast_fifo_reg_B	;
		m_axis_tvalid_fifo_reg_B 	<= m_axis_tvalid_fifo_reg_B ;
		m_axis_tfirst_fifo_reg_B 	<= m_axis_tfirst_fifo_reg_B ;
	end
end

always @(posedge m_axis_aclk or negedge m_axis_areset) begin : B_empty
	if (~m_axis_areset) begin
		// reset
		m_axis_empty_fifo_reg_B 	<=    	1'b1;
	end
	else if(update_A & update_B) begin
		m_axis_empty_fifo_reg_B 	<=		1'b0;
	end
	else if(update_A & (~m_axis_empty_fifo_reg_B)) begin
		m_axis_empty_fifo_reg_B 	<=		1'b1;
	end
	else if(update_B) begin
		m_axis_empty_fifo_reg_B 	<=		1'b0;
	end
	else begin
		m_axis_empty_fifo_reg_B 	<= 		m_axis_empty_fifo_reg_B;
	end
end

always @(posedge m_axis_aclk or negedge m_axis_areset) begin : A_reg_ready_to_trans   
	if (~m_axis_areset) begin
		// reset
		m_axis_trans_en_reg_A 		<=    1'b0;
	end
	else if(update_A & (~m_axis_empty_fifo_reg_B) & (update_B | (~m_axis_tfirst_fifo_reg_B))) begin
		m_axis_trans_en_reg_A 		<=	  1'b1;
	end
	else if(update_A) begin
		m_axis_trans_en_reg_A 		<= 	  1'b0;
	end
	else if(m_axis_tvalid_fifo_reg_A & update_B) begin
		m_axis_trans_en_reg_A 		<= 	  1'b1;
	end
	else begin
		m_axis_trans_en_reg_A 		<= m_axis_trans_en_reg_A;
	end
end

always @(posedge m_axis_aclk or negedge m_axis_areset) begin : store_data_in_A
	if (~m_axis_areset) begin
		// reset
		m_axis_tvalid_fifo_reg_A 	<=    1'b0;
		m_axis_tdata_fifo_reg_A  	<= 	256'b0;
		m_axis_tkeep_fifo_reg_A  	<=   32'b0;
		m_axis_tlast_fifo_reg_A  	<=    1'b0; 
		m_axis_tfirst_fifo_reg_A 	<=    1'b0;
	end
	else if(update_A & (~m_axis_empty_fifo_reg_B)) begin
		m_axis_tdata_fifo_reg_A 	<= m_axis_tdata_fifo_reg_B	;
		m_axis_tkeep_fifo_reg_A		<= m_axis_tkeep_fifo_reg_B	;
		m_axis_tlast_fifo_reg_A		<= m_axis_tlast_fifo_reg_B	;
		m_axis_tvalid_fifo_reg_A 	<= m_axis_tvalid_fifo_reg_B ;
		m_axis_tfirst_fifo_reg_A 	<= m_axis_tfirst_fifo_reg_B ;
	end
	else if(update_A) begin
		m_axis_tvalid_fifo_reg_A 	<=  1'b0 						;
		m_axis_tdata_fifo_reg_A  	<= 	m_axis_tdata_fifo_reg_A  	;
		m_axis_tkeep_fifo_reg_A  	<=  m_axis_tkeep_fifo_reg_A  	;
		m_axis_tlast_fifo_reg_A  	<=  m_axis_tlast_fifo_reg_A  	;
		m_axis_tfirst_fifo_reg_A 	<=  m_axis_tfirst_fifo_reg_A 	;
	end
	else begin
		m_axis_tdata_fifo_reg_A 	<= m_axis_tdata_fifo_reg_A 	;
		m_axis_tkeep_fifo_reg_A		<= m_axis_tkeep_fifo_reg_A	;
		m_axis_tlast_fifo_reg_A		<= m_axis_tlast_fifo_reg_A	;
		m_axis_tvalid_fifo_reg_A 	<= m_axis_tvalid_fifo_reg_A ;
		m_axis_tfirst_fifo_reg_A 	<= m_axis_tfirst_fifo_reg_A ;
	end
end

always @(*) begin
	if(~m_axis_tvalid_fifo_reg_A) begin
		update_A = 1'b1;
	end
	else begin
	case (width_change_step) 
		2'b00: begin
			if(m_axis_tready &/* m_axis_tkeep_fifo_reg_A[0] &*/ (~m_axis_tkeep_fifo_reg_A[8])) begin
				update_A = 1'b1;
			end
			else begin
				update_A = 1'b0;
			end
		end
		2'b01: begin
			if(m_axis_tready & /*m_axis_tkeep_fifo_reg_A[8] &*/ (~m_axis_tkeep_fifo_reg_A[16])) begin
				update_A = 1'b1;
			end
			else begin
				update_A = 1'b0;
			end
		end
		2'b10: begin
			if(m_axis_tready & /*m_axis_tkeep_fifo_reg_A[16] &*/ (~m_axis_tkeep_fifo_reg_A[24])) begin
				update_A = 1'b1;
			end
			else begin
				update_A = 1'b0;
			end
		end
		2'b11: begin
			if(m_axis_tready /*& m_axis_tkeep_fifo_reg_A[24]*/) begin
				update_A = 1'b1;
			end
			else begin
				update_A = 1'b0;
			end
		end
		endcase
	end
end

//step 跳变未考虑到空信号 包括rd
// 帧为空时应该让停到0
always @(posedge m_axis_aclk or negedge m_axis_areset) begin :  cal_the_stop_in_width_change
	if (~m_axis_areset) begin
		// reset
		width_change_step 	<= 2'b0 						;
	end
	else if(update_A) begin
		width_change_step 	<= 2'b0 						;
	end
	else if(m_axis_tready & m_axis_trans_en_reg_A) begin
		width_change_step 	<= width_change_step + 2'b1 	;
	end
	else begin
		width_change_step 	<= width_change_step 	 	 	;
	end
end



always @(posedge m_axis_aclk or negedge m_axis_areset) begin : width_change
	if (~m_axis_areset) begin
		// reset
		m_axis_tvalid 	<=	 1'b0;
		m_axis_tdata  	<=	64'b0;
		m_axis_tkeep  	<=	 7'b0;
		m_axis_tlast  	<=	 1'b0;
	end
	else if(m_axis_tready) begin
		case(width_change_step)
		2'b00: 	begin
			m_axis_tdata 	<= m_axis_tdata_fifo_reg_A[64 * 1 - 1 -: 64];
			m_axis_tkeep  	<= m_axis_tkeep_fifo_reg_A[ 8 * 1 - 1 -:  8];
			if(m_axis_tlast_fifo_reg_A) begin
				// m_axis_tvalid <= (|m_axis_tkeep_fifo_reg_A[ 8 * 1 - 1 -:  8]) & m_axis_trans_en_reg_A/* & (~fifo_empty)*/;
				m_axis_tvalid <= (m_axis_tkeep_fifo_reg_A[ 8 * 1 - 8]) & m_axis_trans_en_reg_A/* & (~fifo_empty)*/;
				//当前8位keep存在0或者当前8位keep为1下一位keep为0
				// m_axis_tlast  <= (((~m_axis_tkeep_fifo_reg_A[ 8 * 1 - 1]) & m_axis_tkeep_fifo_reg_A[ 8 * 1 - 8]) | ((~m_axis_tkeep_fifo_reg_A[ 8 * 1]) & m_axis_tkeep_fifo_reg_A[ 8 * 1 - 1]));
				m_axis_tlast  <= (~m_axis_tkeep_fifo_reg_A[ 8 * 1]);
			end
			else begin
				m_axis_tvalid <= m_axis_trans_en_reg_A /*& (~fifo_empty)*/;
				m_axis_tlast  <= 1'b0;
			end
		end
		2'b01: 	begin
			m_axis_tdata 	<= m_axis_tdata_fifo_reg_A[64 * 2 - 1 -: 64];
			m_axis_tkeep  	<= m_axis_tkeep_fifo_reg_A[ 8 * 2 - 1 -:  8];
			if(m_axis_tlast_fifo_reg_A) begin
				// m_axis_tvalid <= (|m_axis_tkeep_fifo_reg_A[ 8 * 2 - 1 -:  8]) & m_axis_trans_en_reg_A;
				m_axis_tvalid <= (m_axis_tkeep_fifo_reg_A[ 8 * 2 - 8]) & m_axis_trans_en_reg_A;
				//当前8位keep存在0或者当前8位keep为1下一位keep为0
				// m_axis_tlast  <= (((~m_axis_tkeep_fifo_reg_A[ 8 * 2 - 1]) & m_axis_tkeep_fifo_reg_A[ 8 * 2 - 8]) | ((~m_axis_tkeep_fifo_reg_A[ 8 * 2]) & m_axis_tkeep_fifo_reg_A[ 8 * 2 - 1]));
				m_axis_tlast  <= (~m_axis_tkeep_fifo_reg_A[ 8 * 2]);			
			end
			else begin
				m_axis_tvalid <= m_axis_trans_en_reg_A;
				m_axis_tlast  <= 1'b0;
			end
		end
		2'b10: 	begin
			m_axis_tdata 	<= m_axis_tdata_fifo_reg_A[64 * 3 - 1 -: 64];
			m_axis_tkeep  	<= m_axis_tkeep_fifo_reg_A[ 8 * 3 - 1 -:  8];
			if(m_axis_tlast_fifo_reg_A) begin
				// m_axis_tvalid <= (|m_axis_tkeep_fifo_reg_A[ 8 * 3 - 1 -:  8]) & m_axis_trans_en_reg_A;
				m_axis_tvalid <= (m_axis_tkeep_fifo_reg_A[ 8 * 3 - 8]) & m_axis_trans_en_reg_A;
				//当前8位keep存在0或者当前8位keep为1下一位keep为0
				// m_axis_tlast  <= (((~m_axis_tkeep_fifo_reg_A[ 8 * 3 - 1]) & m_axis_tkeep_fifo_reg_A[ 8 * 3 - 8]) | ((~m_axis_tkeep_fifo_reg_A[ 8 * 3]) & m_axis_tkeep_fifo_reg_A[ 8 * 3 - 1]));
				m_axis_tlast  <= (~m_axis_tkeep_fifo_reg_A[ 8 * 3]);
			end
			else begin
				m_axis_tvalid <= m_axis_trans_en_reg_A;
				m_axis_tlast  <= 1'b0;
			end
		end
		2'b11: 	begin
			m_axis_tdata 	<= m_axis_tdata_fifo_reg_A[64 * 4 - 1 -: 64];
			m_axis_tkeep  	<= m_axis_tkeep_fifo_reg_A[ 8 * 4 - 1 -:  8];
			if(m_axis_tlast_fifo_reg_A) begin
				// m_axis_tvalid <= (|m_axis_tkeep_fifo_reg_A[ 8 * 4 - 1 -:  8]) & m_axis_trans_en_reg_A;
				m_axis_tvalid <= (m_axis_tkeep_fifo_reg_A[ 8 * 4 - 8]) & m_axis_trans_en_reg_A;
				m_axis_tlast  <= (/*(~m_axis_tkeep_fifo_reg_A[ 8 * 4 - 1]) &*/ m_axis_tkeep_fifo_reg_A[ 8 * 4 - 8]);
			end
			else begin
				m_axis_tvalid <= m_axis_trans_en_reg_A;
				m_axis_tlast  <= 1'b0;
			end
		end
		default: begin
			m_axis_tdata <= 64'b0;
			m_axis_tkeep <= 8'b0;
			m_axis_tvalid <= 1'b0;
			m_axis_tlast <= 1'b0;
		end
		endcase
	end
	else begin
		m_axis_tdata 	<= m_axis_tdata 	;
		m_axis_tkeep 	<= m_axis_tkeep 	;
		m_axis_tvalid 	<= m_axis_tvalid 	;
		m_axis_tlast  	<= m_axis_tlast  	;
	end
end



endmodule
